(1) Field of the Invention
The present invention relates to the fabrication of a dynamic random access memory (DRAM) device, and more particularly to a method for fabricating polysilicon multilayer stacked capacitors for DRAM cells using a cost-effective dry etching process.
(2) Description of the Prior Art
Dynamic random access memory (DRAM) devices are used for storing digital information. The DRAM consists of an array of memory cells which are accessed by peripheral circuits on the chip for randomly reading and writing information to and from the individual memory cells. The most common memory cell consists of a single current pass transistor, typically a field effect transistor (FET), and a single storage capacitor. With increased circuit density and reduced cell size the capacitor area decreases, and it is important in the DRAM technology to maintain or increase the capacitor area to provide sufficient signal-to-noise margins and reasonable refresh cycle times.
Recently, stacked storage capacitors have drawn considerable attention because they can be built over the FET in a variety of ways to substantially increase the surface area of the capacitors. However, these stacked capacitors generally require additional processing steps and are more costly to manufacture, compared to the more conventional process for making flat stacked capacitors. A schematic cross-sectional view of a simple DRAM cell having a flat stacked capacitor by the prior art is shown in FIG. 1. The DRAM cell consists of a field effect transistor formed from a gate oxide 14, a polysilicon gate electrode 20, lightly doped source/drains 16 and source/drain contact areas 17. Formed concurrently from the same polysilicon layer 20 are the word lines 20' on the field oxide (FOX) 12. A first insulating layer 22 and sidewall spacers 24 insulate the gate electrodes 20 (and word lines 20'). Self-aligned contact openings 3 are etched in a second insulating layer 26 to form the capacitor node contact. A second polysilicon layer is deposited and patterned to form the bottom electrode 30 for the flat stacked capacitor. A thin insulating layer 32 having a high dielectric constant is formed on the bottom electrode 30 and a polysilicon top electrode 34 is deposited and patterned to complete the flat capacitor on the DRAM cell.
Several methods of making more complex stacked capacitors with still more capacitance are reported in the literature. For example, Sato et al., U.S. Pat. No. 5,416,037, teaches a method for making a multilayer stacked capacitor using a multilayer of undoped polysilicon and oxygen-rich polysilicon in which the oxygen-rich polysilicon is selectively and isotropically etched to form a fin-like capacitor. In U.S. Pat. No. 5,441,909, Kim describes another method for making a fin-shaped capacitor by depositing and patterning a polysilicon layer over a sacrificial oxide layer composed of phosphosilicate glass (PSG). The oxide is then removed to form a fin-like bottom electrode capacitor structure. Kim further deposits a second polysilicon layer and etches back to form a double-fin structure. Still another method of making stacked capacitors is taught by Chou in U.S. Pat. No. 5,286,668, in which a second embodiment is described using a multilayer comprised of an undoped polysilicon, a doped polysilicon and another undoped polysilicon. The polysilicon layers are deposited sequentially and the second layer is in-situ doped during the deposition. The multilayer is then patterned to form the bottom electrode of the capacitor, and the doped polysilicon is then etched in a hot phosphoric acid solution to selectively remove portions of the doped polysilicon to form a double-fin-shaped structure. However, this wet-etch process requires moving the wafers from one dry processing system to a wet station, which increases the probability of contamination and increases process time and manufacturing cost.
Therefore, there is a strong need in the industry to reduce the manufacturing cost by eliminating the wet-etch processes in favor of dry-etch processes and for automating the process in multichamber processing. The use of dry etching eliminates large volumes of waste chemicals and costly reclamation systems, and further reduces manufacturing costs.